This invention relates to semiconductor processes and more particularly to a method to calculate semiconductor yield loss.
Yield reliability and loss is an important part of semiconductor manufacturing. Integrated circuits must be able to be produced in large quantities at low cost. The integrated circuits must also be capable of performing their intended function throughout their lives. To meet these requirements, tests are performed to find the causes of fails in order to eliminate them, as well as to identify circuits that will not perform up to design and customer expectation. The data from testing can be used to perform yield calculations.
Yield and yield loss calculations, in particular, allow semiconductor manufacturers to perform redundancy calculations. These calculations are utilized to decide how redundant or extra parts of a semiconductor device (e.g., redundant rows or columns in a semiconductor memory array) can be allocated to replace defective parts of the device. Because redundant parts are limited in number, it is important for the manufacturer to determine the most efficient utilization of these redundant parts. For example, if xe2x80x9cfail twoxe2x80x9d (i.e. the failure at test number two) is the result of xe2x80x9cfail onexe2x80x9d (i.e. the failure at test number one) then utilizing the redundant parts to cure fail one will also cure fail two. Thus, understanding the relationship between fails and their sequence is important. Likewise, utilizing redundant parts to cure the most prevalent fails will provide best utilization of the limited number of redundant parts. There should be therefore, yield and yield loss calculations that will provide accurate results for assessment of redundant part usage. There should also be yield loss calculations which take into account the relationship between fails.
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by the present invention that is a method for calculating yield losses.
In one aspect, the present invention provides for a method of calculating yield loss of semiconductor wafers which are tested with a test sequence to derive a total fail region count for each of the wafers, the semiconductor wafers having multiple chips thereon. The method comprises calculating a fail region count for each of the tests in the test sequence, calculating a test sequence limited yield loss for each of the semiconductor wafers, and apportioning the test sequence limited yield loss to selected ones of the tests in the test sequence. The method further comprises analyzing the test sequence limited yield loss for determining reparability of one or more of the chips.
In another aspect the present invention provides for a computer program product for calculating the yield loss of semiconductor wafers. In this aspect, the product comprises a computer-readable medium; and computer executable instructions contained on the computer-readable medium. The computer executable instructions provide for performing the steps of calculating a fail region count for each of a plurality of tests in a test sequence and calculating a test sequence limited yield loss for each of the semiconductor wafers. The instructions further provide for apportioning the test sequence limited yield loss to selected ones of the tests in the test sequence and analyzing the test sequence limited yield loss for determining reparability one or more of the chips.
One advantage of a preferred embodiment of the present invention is that it provides a method of identifying fails for efficient allocation of yield loss.
Another advantage of a preferred embodiment of the present invention is that it provides a method of assigning a yield loss to a certain test by means of a statistical breakdown of the experienced yield loss for a large number of tests as opposed to assigning a yield loss by individual reparability calculations.
An advantage of a preferred embodiment of the present invention is that it takes into account the number of unique fails a test may have found.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the concepts and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.